Low-side Current Detection | High-side Current Detection

1. Design Example of Low-side Current Detection

Use the S-19630A and R1 - R4 to configure a low-side current detection circuit.

Current Sensor Design Specifications

• Shunt resistance value RSHUNT:
  1mΩ
• Current detection range:
  IDET = 0A to 20A
• Current detection accuracy
  Offset error:
  ±0.1A or less (at IDET=0A)
  Gain error:
  ±0.5% or less (±0.1A or less at IDET=20A)
• Current detection frequency:
  1kHz or more
• S-19630A power supply voltage VDD:
  5.0V
• S-19630A gain bandwidth product GBP:
  1.2MHz
• S-19630A load capacity CL1:
  0.22μF
• S-19630A output voltage (at IDET=0A):
  0.5V(=REF voltage)
• Microcontroller AD converter measurement range:
  0V - 5.0V
• Cut-off frequency Fc of input noise elimination filter:
  10kHz

Design Procedure

Design procedure 1. Gain setting

Set the gain so that the output pin (OUT) voltage of the S-19630A is 0.5V at IDET=0A and 5.0V at IDET=20A.
Gain=(5.0V-0.5V)/(20mV - 0mV)=225 times
Due to the S-19630A gain bandwidth product (1.2MHz) and the set gain (225 times), the current detection frequency is 5.3kHz.

Design procedure 2. R1 - R4 setting

Set R1 to R4 from Gain.
Since setting a high resistance value for R1 and R2 will increase noise and measurement error, set a resistance somewhere between 100Ω to 1kΩ.
Set R1 and R2 to 120Ω for now. Thus, R3=R4=120Ω×225 times=27kΩ.

Design procedure 3. Select R1 - R4 resistance ratio accuracy from the current detection accuracy that should be achieved.

Offset error is 0.10A and gain error is ±1.0% when a resistance ratio accuracy of 0.5% is selected: Does not meet the specification.
Offset error is 0.06A and gain error is ±0.2% when a resistance ratio accuracy of 0.1% is selected: Meets the specification.
Select a resistor with a resistance ratio accuracy of 0.1% from the current detection accuracy specifications.

Design procedure 4. Input noise elimination filter constant (R1, R2, C1, C2) settings

Set C1 and C2 from the noise elimination filter cut-off frequency Fc (10kHz) and R1=R2=120Ω.
From Fc=1/(2×π×R1×C1)
set C1=C2＝1/(2×π×R1×Fc)= 1/(2×π×120×10k)=0.15μF

Design procedure 5. Oscillation countermeasures for the S-19630A

1. Oscillation countermeasure 1
The gain setting and the load capacitance CL1 setting of the output pin (OUT) may make oscillation countermeasures necessary.
The maximum load capacitance CL (470pF) stated on the S-19630A datasheet is the maximum load capacitance value that permits stable operation even when a connection is made to the output pin and gain is set to 1 time. As shown in the following equation, maximum load capacitance CL varies with the gain setting.
CL=470pF×Gain
When the CL1 load capacitance of the S-19630A is larger than CL, oscillation countermeasures are required.

In this design example,
CL1=0.22μF
CL=470pF×225 times=0.11μF
As this makes CL1 larger than CL, oscillation countermeasures are required.

Oscillation countermeasures
(1)Change the capacitance to 0.1μF, for example, to set CL1 to a value lower than 0.11μF. Or,
(2)Insert a 100Ω resistor R5 in series with CL1.

An R5 (100Ω resistor) is inserted in this design example.

2. Oscillation countermeasure 2
The gain setting and R1 (=R2) and C1 (=C2) settings may make oscillation countermeasures necessary.
Oscillation countermeasures are necessary under the following conditions.
R1×C1>(1+gain)/(2π×1.2MHz×10)

In this design example,
R1×C1=120×0.15μ=18μ
(1+gain)/(2π×1.2MHz×10)=3μ
As this makes R1×C1>(1+gain)/(2π×1.2MHz×10), oscillation countermeasures are required.

Oscillation countermeasures
Connect capacitor C3 satisfying the following equation to R3 in a parallel connection.
C3>C1/(3×gain+2)
In this design example, the gain (225 times) and C1 (0.15μF) so
C3>222pF
And for that reason, connect C3 (330pF).

*Method for confirming stability free from oscillation
It is recommended to use an oscilloscope to check the signal waveform of the OUT pin to confirm that the signal is stable and free from oscillation.
Note that it may not be possible to correctly confirm that a signal is stable and free from oscillation when checking the waveform of a signal from the OUT pin that has gone through a filter or when measuring an OUT pin signal using a volt meter (averaged processed).

ABLIC's operational amplifier products are provided with circuit design consultation services, including circuit simulation at the customer’s circuit design stage. If you are interested, feel free to call our sales office anytime.

Current Sensor Design Results

• Shunt resistance value RSHUNT:
  1mΩ
• Current detection range:
  IDET = 0A to 20A
• Gain:
  225 times
• S-19630A output voltage:
  0.5V(at IDET=0A), 5.0V(at IDET=20A)
• Current detection accuracy
  Offset error:
  ±0.06A or less (at IDET=0A)
  Gain error:
  ±0.2% or less (±0.04A or less at IDET=20A)
• Current detection frequency:
  5.3kHz
• Transient response characteristics (OUT voltage waveform after change from IDET 0A to 15A)

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